Intel Corporation v. Pact XPP Schweiz AG
Docket No. 2022-1037 (IPR 2020-00518) (https://cafc.uscourts.gov/opinions-orders/22-1037.OPINION.3-13-2023_2093578.pdf)
NEWMAN, POST, HUGHES
March 13, 2023
Brief Summary: Board IPR finding that Intel did not show PACT’s claims unpatentable for obviousness reversed as prior art shows the claimed limitations and the motivation to combine shown under the “known-technique” rationale.
Summary: Intel appeal USPTO Board finding that Intel failed to show claim 5 of PACT’s US 9,250,908 relating to multiprocessor systems and how the processors access data unpatentable as obvious in view of the prior art (Kabemeto and Bauman). This opinion first explained that multiprocessor systems store data in a main memory and various cache memories that “are closer to the processors, allowing the processors quicker access to the data available in a given cache”, and that “a system can use multiple cache levels, where a primary cache is closer to the processer but can store less data than a further-away secondary cache.” Those cache memories must be monitored “to maintain cache coherency” by, e.g., “‘snooping’ along a shared ‘bus’” or “using a global, segmented secondary cache.” ‘908 claim 5 depends from claim 4, so Intel needed to show the prior art showed all the limitations of claims 4 and 5 (Vectra, FC 1998). Claim 4 includes an “interconnect system interconnecting…separate cache segments with each of the processors” with interconnection of “each . . . separated cache segment with neighboring separated cache segments”, which Intel alleged was shown by the figures of the prior art (e.g., “[a] person of ordinary skill…would connect Bauman’s global, segmented secondary cache ‘to [Kabemoto’s] snoop bus 22 on the outside of [processor] element 14-1’ to reach a system with the claimed separated cache and interconnect system”). PACT did not dispute that argument, but “that Intel failed to demonstrate a motivation to combine Kabemoto and Bauman”. The FC panel wrote that “the Board purported to ‘agree’ with PACT that Intel failed to demonstrate that the prior art disclosed the segment-to-segment limitation” of claim 4, and that “PACT counsel admitting ‘in all candor’ that PACT ‘did not make this . . . argument’ before the Board.” The Board also agreed with PACT that Intel failed to show the motivation to combine the references to prove claim 4 to be unpatentable, and therefore challenged claim 5 was patentable. The FC panel agreed with Intel that “substantial evidence does not support the Board’s determination that the prior art fails to disclose” claim 4 or that there was no motivation to combine the references. In FN2, it also wrote that the Board’s incorrect conclusion may have come from its misconstruction of the claim terms but that neither Intel nor PACT raised that issue in this appeal. Regarding the motivation to combine, the FC panel explained that “in many cases[,] a person of ordinary skill will be able to fit the teachings of multiple patents together like pieces of a puzzle” which is “why the motivation-to-combine analysis ‘need not seek out precise teachings directed to the specific subject matter of the challenged claim, for a court can take account of the inferences and creative steps that a person of ordinary skill in the art would employ’”, “‘universal’ motivations known in a particular field to improve technology provide ‘a motivation to combine prior art references even absent any hint of suggestion in the references themselves’”, and “if a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond his or her skill” (the “known-technique” rationale; “if there’s a known technique to address a known problem using ‘prior art elements according to their established functions,’ then there is a motivation to combine” and “[i]t’s not necessary to show that a combination is the best option, only that it be a suitable option”) (KSR, US 2007). Here, the FC panel agreed with Intel’s motivation to combine the references since, e.g., “a person of ordinary skill would ‘recognize that’ such a cache ‘would improve similar’ multiprocessor systems…by addressing that same cache coherency problem.” As “[n]othing more is required to show a motivation to combine under KSR”, the FC panel reversed the Board, noting that the Board still must “address any remaining dispute about the patentability of claim 5.”